Introducing JamaicaFPGA
David Beberman
Embedded World 2016, Nuremberg


Introducing JamaicaFPGA

Enabling Software-Defined Hardware with Aicas Jamaica and Xilinx SDSoC Toolchains on the Xilinx Zynq Ultrascale+ MPSoC

A field-programmable gate array (FPGA) is an in­tegrated circuit designed to be configured by a cus­tomer or a designer after manufacturing – hence "field-pro­grammable". The FPGA configuration is generally specified using a hardware description lan­guage (HDL), similar to that used for an application-specific integrated circuit (ASIC). (Circuit diagrams were pre­viously used to specify the configuration, as they were for ASICs, but this is increasingly rare.) FPGAs contain an array of programmable logic blocks, and a hierarchy of reconfigurable intercon­nects that al­low the blocks to be "wired together", like many logic gates that can be inter-wired in different configu­rations. Logic blocks can be configured to perform complex combinational func­tions, or merely simple logic gates like AND and XOR. In most FPGAs, logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory.

- Wikipedia

Xilinx Zynq Ultrascale+ MPSoC
Xilinx's new Zynq Ultrascale+ MPSoC combines FPGA technology with multicore application pro­cessors (APU) and fault detection capable realtime processors (RPU). A complete system design us­ing the MPSoC may incorporate multiple software processes on the APUs, multiple software pro­cesses on the RPUs, multiple processes running on soft CPUs implemented on the FPGA fabric, and multiple FPGA logic blocks.

The Problem: System Complexity
This is truly an amazing level of integration of features and flexibility on a single chip. At the same time, the complexity of such a system design may quickly become unmanageable.

As an example consider the following conceptual design:

  • The APUs are running an SMP Linux OS.
    • There are 4 multithreaded processes written in C/C++ loaded on the Linux OS
      • The processes are subject to the Linux completely fair scheduler (CFS)
    • The Linux OS is configured for Linux realtime threads
      • Several of the processes schedule realtime threads in addition to CFS threads
  • The RPUs are running a flat memory model RTOS (e.g. VxWorks)
    • There are 4 tasks written in C/C++ loaded on the RTOS, each with several threads to be scheduled as Round Robin or FIFO at fixed priorities
    • There are several interrupt handlers responding to system events
  • The FPGA is loaded at startup with a Microblaze Linux
    • 4 processes written in C/C++ are loaded on the Microblaze Linux
  • The FPGA is loaded at startup with gate logic realizing several functions written in VHDL, Verilog or C/C++ code synthesized by the SDSoC/Vivado toolchain
    • FFT
    • Time domain filters
    • Data filters

In summary there are 4 C/C++ processes running on a multicore SMP Linux with MMU protection, 4 C/C++ processes running on a multicore VxWorks RTOS without MMU protection, 4 processes run­ning on singlecore Microblaze Linux with MMU protection, and several functions realized in FPGA logic that may interface with any and all of the processes running on any of the CPUs.

The question is, from a software and system defect viewpoint, is this system realizable to a given sys­tem assurance level, with a reasonable project schedule, and a reasonably sized development team.

The C/C++ code for each OS and CPU configuration has implementation characteristics that are unique to the OS, CPU and compiler toolchain. That is, the code written for the APU Linux OS may not be portable to the RPU VxWorks OS, or the Microblaze Linux OS, or even the realtime threads on the APU Linux OS. Further, as has been well documented, and any C/C++ programmer will immediately agree with, C/C++ code is prone to many types of memory errors, of which some are “ghost” bugs that can be virtually impossible to recreate in lab conditions. Although the SDSoC toolchain translates C/C++ code sections to FPGA logic, the remaining CPU hosted code continues to be subject to the in­herent fragility of the C/C++ programming languages. It can be argued that multiple errors may cause “cascading failures” such that locating the root cause of a failure be­comes exponentially more difficult.

At the start of a project, which plans to make use of the breadth of the features of the MPSoC, pro­jecting scheduling, resources and costs can be challenging. Planning for ongoing updates, new fea­tures and maintenance after project completion can also be challenging. Engineering management in general is risk averse with good reason. The critical question is how can the developers make use of the fea­tures of the MPSoC while engineering management tracks to its project plan.

What is needed is a common approach to CPU hosted and FPGA hosted code development that elimi­nates programming language fragility.

What is needed is a common approach to CPU hosted and FPGA hosted code development that elimi­nates OS and CPU dependencies enabling transparent porting.

What is needed is a common approach to CPU hosted and FPGA hosted code development that lends itself to emulation for unit and system testing when target hardware is unavailable.

The Solution: An “All Programmable” Highlevel Language Toolchain
There is a programming language solution that eliminates memory error fragility.
There is a compilation toolchain that eliminates OS and CPU dependencies.
There is a runtime that enables emulation unit and system testing without target hardware.

Its name is Jamaica, and includes the Jamaica compilation toolchains, the JamaicaVM deterministic re­altime runtime and supports all Java bytecode languages (e.g. Java, Scala, Jython, JRuby, etc.).

And now, with the combination of Aicas and Xilinx technology, there is a technology that synthe­sizes FPGA logic directly from highlevel languages and transparently integrates CPU hosted code with FPGA realized code. Introducing JamaicaFPGA the only compilation toolchain that generates FPGA logic directly from Java bytecodes.

Using JamaicaFPGA, execution jitter requirements beyond the bounds of CPU instruction execution can be realized in FPGA logic without coding changes.

Using JamaicaFPGA, execution throughput requirements beyond the bandwidth of CPU perfor­mance can be realized in FPGA logic without coding changes.

Using JamaicaFPGA, power and heat savings enabled by FPGA logic implementations as opposed to CPU implementations can be realized without coding changes.

Jamaica is the all programmable highlevel language toolchain solution to the system complexity prob­lem.

The JamaicaVM runtime is hosted on APU Linux OS, the RPU VxWorks RTOS and the Microblaze Linux OS. The runtime environment provides a full, but open and flexible abstraction common to all CPU and OS combinations. It includes the Realtime Specification for Java (RTSJ) which pro­vides safe access to memory mapped register files. The identical Java Archive (JAR) file will load and run on all of the runtime environments. Thus the developer does not need to modify source code to target the APU, RPU or Microblaze CPUs.

The Jamaica Builder and Jamaica JAR Accelerator translate the Java bytecodes from JAR files to ma­chine instructions. Both compilers support the APU ARM53, the RPU ARMR5 and the Microb­laze in­struction sets. The result is no code changes, no porting, no hidden compiler, runtime, CPU or OS de­pendencies.

JamaicaFPGA carries the runtime environment abstraction to the FPGA fabric. JamaicaFPGA takes as input the identical Java bytecodes from JAR files as Jamaica Builder and Jamaica JAR Accelera­tor. In­tegration between code running on the APU, RPU, Microblaze and the FPGA synthesize code is trans­parent at the source code level.

The combination of these features realizes an “All Programmable” Highlevel Language Toolchain. Blurring the line between software and hardware, the combination of Aicas Jamaica and Xilinx SD­SoC toolchains and Xilinx MPSoC FPGA technology opens a new era in computing system design.



Xilinx, Zynq, Ultrascale+, MPSoC, SDSoC are trademarks of Xilinx, Inc.
Aicas, JamaicaVM, Jamaica JAR Accelerator, Jamaica Builder, JamaicaFPGA are trademarks of
aicas GmbH.


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