Publications

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Two Generalisations of Roşu and Chen’s Trace Slicing Algorithm A

Published/Presented at: 
5th International Conference, RV 2014, Proceedings, B. Bonakdarpour and S.A. Smolka, RV 2014, LNCS 8734, pages 15–30, 2014 ©
Author: 
Clemens Ballarin

Roşu and Chen's algorithm is at the core of the JavaMOP runtime verification tool.  The paper presents significant generalisations over the original algorithm while maintaining its unprecedented performance.

Real-Time Specification for Java Update (JSR 282 Progress)

Published/Presented at: 
JTRES 2013, Karlsruhe, Germany
Author: 
James J. Hunt

Real-Time Specification for Java Update (JSR 282 Progress)

A new I/O model for the real-time specification for Java

Published/Presented at: 
JTRES 2012 - Copenhagen, Denmark
Author: 
James J. Hunt

The Real-Time Specification for Java (RTSJ) does not only provide features for realtime programming but also for direct device access. Both reading and writing to a device and reacting to external signals are supported. Unfortunately, the APIs provided have two major drawbacks: since a single class is used to access all types of I/O devices, it is hard to provide an efficient implementation; and there is no mechanism for the user to add new external signals.

Graph Transforming Java Data

Published/Presented at: 
FASE 2012 - 15th International Conference on Fundamental Approaches to Software Engineering, Tallinn, Estonia
Author: 
Maarten De Mol, Arend Rensink and James J. Hunt

The Practical Application of Formal Methods: Where is the Benefit for Industry?

Published/Presented at: 
FoVeOOS 2011 - 2nd International Conference on Formal Verification of Object-Oriented Software, Turin, Italy
Author: 
James J. Hunt

Abstract

Multicore for RealTime and Safety Critical Software: Avoid the Pitfalls

Published/Presented at: 
MultiCore Expo - The 6th Annual Multicore Developers Conference 2011, San Jose, CA, USA
Author: 
Dr. Fridtjof Siebert, Dr. James J. Hunt

The move towards multicores is so strong that real-time and safety-critical applications will make use of multicores and have to adapt to the rules dictated by multicore hardware, while off-the-shelf multicore hardware is optimized for average-case throughput. This talk focusses on the impact this move to multicores has on real-time and safety-critical code. The software developer has to be aware of the effects of cache structures and memory models to understand the consequences on performance and correctness of his code.

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